Federal Intelligence Researchers Boost Chip Security
IARPA looks to develop a "split-manufacturing" process that bakes intellectual property protection inside microprocessors.
Slideshow: 50 Most Influential Government CIOs
(click image for larger view and for slideshow)
The research arm for the federal intelligence community is seeking to create a more secure way to develop microprocessors that bakes protection right into the chips.
Through a program called Trusted Integrated Chips (TIC), the Intelligence Advanced Research Project Agency (IARPA) aims to develop what it's calling a "split-manufacturing" process for chips to ensure intellectual property protection is built into them.
"It is desirable for the U.S. academic community and the U.S. industrial base to have open and assured access to obtain the highest performance integrated circuits and [systems on a chip] while ensuring that components have been securely fabricated according to design," according to a broad agency announcement (BAA) seeking research ideas for the program.
Through this process, chip fabrication is split into front-end-of-line (FEOL) and back-end-of-line (BOEL). The former fabricates transistor layers in offshore foundries, while the latter consists of metallizations that are fabricated in "trusted U.S. facilities," according to IARPA. Those working on the FEOL part of the process will not have access to information about the design intention of the chips, the agency said.
[With a year under her belt, Teri Takai looks to introduce new technologies while strengthening the Defense Department's cyber defenses. Learn more about the Pentagon CIO's Tech Revamp: 4 Priorities.]
In this way, the TIC program can achieve the "highest performance possible" in integrated circuits while obtaining "near 100% assurance that designs are safe and secure--not compromised with malicious circuitry," according to IARPA. The agency also wants to ensure design and intellectual property security.
IARPA is seeking demonstrations of its split-manufacturing concept for the five-year, three-phase program in the following design applications: mixed signal, photonics-CMOS, MEMS-CMOS, power-CMOS, RF CMOS, memory-CMOS and Josephson junctions-CMOS, according to the BAA.
Sandia National Laboratories will coordinate all FEOL and BEOL processing for the program, the agency said, while the University of Southern California Information Sciences Institute (USC/ISI) will carry out fabrication runs.
IARPA's interest in building security into chips is in line with other efforts by the government--in particular the Department of Homeland Security (DHS)--to more securely lock down the technology supply-chain process.
Earlier this year, a DHS executive acknowledged the threat of pre-existent malware on imported electronic and computer devices sold within the United States, bringing light to a persistent problem of component-level threats the feds have been trying to mitigate for some time.
Join us for a roundup of the top stories on InformationWeek.com for the week of December 14, 2014. Be here for the show and for the incredible Friday Afternoon Conversation that runs beside the program.