Commentary

Alexander Wolfe
 

AMD Launches Long-Awaited Quad-Core Barcelona

The long wait for AMD's first quad-core processor is over, with the introduction today of Barcelona. Amid the over-the-top press coverage, the important question to ask is: How does this chip perform in comparison to Intel's quad Xeons?

The long wait for AMD's first quad-core processor is over, with the introduction today of Barcelona. Amid the over-the-top press coverage, the important question to ask is: How does this chip perform in comparison to Intel's quad Xeons?Equally important, the debut of Barcelona marks the beginning of what I believe will be a huge price war between Intel and AMD. Expect Intel to cut its prices to the bone, putting pressure on its smaller competitor.

At the end of the day, though, the beneficiaries will be end users, who'll have a bevy of hot chips to choose from. (Remember that Barcelona and Xeon are server processors. AMD will introduce its Phenom desktop quad later this year; those chips will compete against Intel's heavy duty lineup of Core quad devices, already shipping.)


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So what exactly do we have in Barcelona? The processor contains upwards of 450 million transistors and is fabricated in 65-nm technology. This puts AMD at something of a disadvantage vis-'-vis Intel, which will ship 45-nm quad core processors later this year. In terms of chip construction, smaller is better because its enables lower power operation. It also allows the chip vendor to get higher yields, by placing more processors on each of the large 300-mm wafers on which the chips are made before they're sliced off and individually packaged.

Barcelona marks the introduction of a completely new on-chip architecture from AMD. Called 10h, it offers a host of improvements, including:

  • Beefed up floating-point support. Earlier processors had 64-bit floating-point execution units. Because of 10h, AMD will be able to equip Phenom and Barcelona with 128-bit floating-point units, if it so chooses. The wider design will double the performance of floating-point vector operations.

  • Instruction-fetching improvements. The fetch window has been widened to 32 bytes from 16 bytes. This will allow the processor to handle a complete sequence of three large instructions per cycle.

  • Large page support. As mentioned earlier, the 10h processors now support 1-GB paging. The feature provides a big benefit to applications, such as multimedia, which operate on large data sets.

  • Instruction-set improvements. These include the addition of two advanced bit-manipulation instructions, which operate on general purpose registers

  • Virtual machine optimizations. The 10h architecture includes many improvements to boost the performance of AMD's virtualization technology, as well as compiler-related optimizations.

    That's the preliminary scorecard. For more perspective, listen to my podcast with AMD vice president Randy Allen.



    This die shot identifies the different functional units of Barcelona, AMD's upcoming quad-core Opteron. (Click picture to enlarge.)


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