Processor maker ARM announced Tuesday the next generation of its interface and protocol specification, AMBA 4, which enables system-level cache coherency that supports communications between cores.
AXI Coherency Extensions (ACE) enable the AMBA 4 protocol to support multicore computing through system-level cache coherency across clusters of multicore processors, such as the ARM Cortex-A15 and Mali-T604 graphics processors.
Through ACE, AMBA 4 enables coherency that maintains the consistency of data stored in local caches as a shared resource. This helps multicore computing applications to efficiently maintain the consistency of data stored in local caches of a shared resource.
The AMBA 4 helps increase performance and power efficiency of complex heterogeneous system-on-a-chip (SoC) designs, and is designed to address next-generation computing across mobile, home, networking, and gaming applications, ARM stated.
"What we have done is create coherency in dedicated hardware and that means the software community has a more standard way of programming for CPUs and graphics processor engines for a compute subsystem comprising GPUs and CPUs," said Michael Dimelow, director of marketing for ARM, in an interview.
AMBA is a standard on-chip interconnect methodology that is supported by a majority of the digital electronics industry. The standardized interface allows compatibility between Internet protocol components from different design teams or vendors. The AMBA 4 specification was driven by a group of semiconductor, electronic design automation, and verification vendors, including Arteris, Cadence, Jasper, Marvell, Mentor, Sonics, ST Ericsson, Synopsys, and Xilinx.
The introduction of memory barriers throughout the memory subsystem allows system architects to provide optimal instruction ordering to improve system performance. Distributed virtual memory signaling extends memory virtualization--introduced with the latest ARM architecture and the Cortex-A15 processor--to the system memory management units to make more efficient use of external memory and provide the ability for multiple operating systems to share hardware resources under an appropriate hypervisor.
"Whenever there is an opportunity to move a labor-intensive function into the dedicated hardware, then we try to encourage industry to do that," Dimelow said. "The way we do that is through specifications like AMBA to encourage people to implement those labor-saving functions into hardware."
The latest specification is the second phase of the AMBA 4 protocol. Phase one was launched in 2010 and included a definition of an expanded family of AXI interconnect protocols. So far, more than 4,000 engineers from 2,500 unique businesses and organizations have downloaded the first phase, ARM stated.
"Marvell has been an active contributor to the standardization of hardware coherency within the AMBA 4 specification," said Hongyi Chen, VP of engineering in processor design at Marvell Semiconductor, in a statement. "A key benefit of AMBA 4 ACE is the provision of a development ecosystem with a standard protocol that makes future hardware design far easier. This protocol enables transparent management of cache coherency that removes a significant burden from software engineers."
Last year Marvell introduced a triple-core ARM processor for smartphones and tablet computers that the company claims has the horsepower to drive full high-definition 3-D video while maintaining long battery life.
ARM's chips are currently used in most of the world's smartphones and tablets, with ARM licenses used by chipmakers Nvidia, Samsung, Texas Instruments, and Qualcomm. Many current smartphone and tablet processors are derived from ARMs current Cortex-A9 design. Smartphones and tablets will feature the ARM Cortex-A15 processor beginning in late 2012 or early 2013, according to ARM officials.
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