The chipmaker's new transistor design leapfrogs competitors for now; here's how it works and why all computer chips will eventually use the technology.
Intel announced on Wednesday that it had made the production of 3-D transistors a commercially viable reality and further claimed that in so doing, the company would continue to meet or beat the promise of Moore's Law for years to come. Intel cofounder Gordon Moore realized that through various innovations in process, chemistry, and geometry, it was predictable that transistors would shrink and that products built on them would become more powerful, less costly, or both. But that doesn't mean that adhering to Moore's law is easy. It requires constant research and investment to find and commercialize innovations that allow for smaller and smaller transistors.
As they're used in integrated circuits like microprocessors, transistors can be thought of as switches, when they're on, current flows, when they're off, no current flows. The goal of the transistor designer is to make the perfect switch, lots of power can flow when turned on, absolutely no power flows when turned off, and the switch can change states very quickly, requiring very little power to do so. Generally, the smaller the transistor, the less power it needs to do its thing, but as transistors get very small, you can think of them as behaving less like a switch, and more like a valve. Valves take time to close, they can be leaky, and the more stuff (water or whatever) that you want to flow through the valve, the bigger it has to be.
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Previous state of the art transistors on the left, new 3-D transistors on the right
Using the valve analogy, you can immediately understand some truisms about transistors. Leaky ones are bad, and smaller ones can usually open and close faster than bigger ones, but they let less water (or current in the case of transistors) through. Further, a valve that's designed to close very tightly can often be slower to close than one that's a little bit leaky. These are the sorts of trade-offs that integrated circuit transistor designers have to deal with. They chose the geometry of the transistor, the process for making it and the materials that will be used to meet speed, power consumption, and cost constraints.
Chips in the first PC CPUs were designed in the early 1970s, had about 3,500 transistors, and used a 10-micrometer manufacturing process. Now, chips have north of 3 billion transistors on a chip and use a process closing in on 10 nanometers, making today's transistors almost a million times smaller than those from the 1970s. To make that happen, almost everything about chip making has changed in those 40 years, but one thing that hasn't--until now--is the planar nature of the process.
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Classic planar transistor
Classical chip manufacturing starts with substrate, usually a wafer cut from a silicon ingot. To make transistors on that wafer, manufacturers go through processes of depositing very specialized materials and then etching some that material off. Each layer's material is different, and each etching uses a different mask to produce the desired geometry. The process results in a planer design--if you want more current to flow, you make a wider channel for it. If you want valves that close very quickly, you make them as small as possible, and so on. The valve or gate is a material that sits across the channel. Depending on the charge state of the gate, the channel material conducts better or worse. When a transistor is off (no electrical field present), some current still gets across the channel. This is referred to as leakage current, and even a little of it is very bad news. While leakage current is a tiny amount in one transistor, if you multiply it by a billion or so transistors, it adds up. In servers it results in heat and in handheld devices it results in reduced battery life.
Basically, the smaller the channel, the more you have to worry about leakage current. So as manufacturers go to smaller gates, they have to be very careful to get the geometry right--meaning the etching process needs to be good, and they have to resort to more exotic materials to keep leakage current small--two of the techniques used to limit leakage include strained silicon and high-k dielectrics.
Because the goal is to always pack more transistors on a chip, you can't make the channel wider, so as any New York City developer knows, the answer is to go vertical. Doing so creates more surface area between the channel and gate, and therefore allows better control of its characteristics. Besides allowing for better control of leakage current, going vertical also allows for faster operation of the gate. It can now close off the channel from three sides--hence the name tri-gate--rather than just one. Alternatively, operating voltage can be reduced, which further saves power when the transistor--and hence device--is in its active state.
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Intel's 3-D or tri-gate transistor
While conceptually elegant, the notion of going up has one big problem. It doesn't work all that well in the classic process of depositing and etching away material to create the integrated circuit. This, along with other materials challenges, is what Intel has apparently solved in a way that is commercially viable. So viable, that it says using its 3-D design incurs no more than a 3% increase in cost.
Intel has a lead on this technology. It appears that competitors are a good 24 months behind in bringing it to market. With the new technology, transistor-operating voltages can go down thus saving power, while maintaining performance. Intel, like its competitors are driving toward 14 nm processes, which will almost certainly require 3-D transistor geometry to keep power dissipation low. All in all, 3-D transistors are an enabling technology for all chipmakers. The good news all-around is that Moore's law marches on.
Art Wittmann is director of InformationWeek Analytics, a portfolio of decision-support tools and analyst reports. You can write to him at email@example.com.
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