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IBM And AMD Unveil Breakthroughs In 45-Nanometer Chip Production

The companies say they've successfully combined cutting edge techniques like immersion lithography and ultra-low-k interconnect dielectrics.

IBM and Advanced Micro Devices on Tuesday jointly disclosed breakthroughs in the microchip manufacturing process that they say puts them ahead of competitors in the race toward 45-nanometer chip production -- a significant industry milestone that will lead to faster, more efficient computers.

The companies, which have partnered in several key areas of chip design since 2003, say that in prototype manufacturing they've successfully combined cutting-edge techniques such as immersion lithography, in which chips are etched by light while under water to better focus the beam, and ultra-low-k interconnect dielectrics, which uses insulating materials to prevent electrical interference between the individual transistors on a chip.

As a result, IBM and AMD said they expect to begin shipping 45-nanometer products based on these technologies by mid-2008. The current state of the art for most chip production is 65 nanometers. The measurement refers to the average width of subcomponents on a chip. A nanometer is one billionth of a meter -- many times smaller than a hair's width.

Chipmakers such as IBM and AMD, along with competitors like Intel, count on their ability to continually shrink component sizes to deliver successive generations of products that can outperform their predecessors. IBM and AMD claim that an SRAM (Static Random Access Memory) chip in development using their enhanced 45-nanometer technology shows a 15% performance improvement over previous versions.

But with transistor components already sub-microscopic, future size reductions are becoming increasingly difficult to achieve. The etching of circuits onto silicon becomes trickier and densely packed transistors can start interfering with each other by generating electrical cross-talk. That's why manufacturers are searching for new techniques that overcome the inherent limitations of nano-scale production.

In addition to using low-k materials and innovations such as immersion lithography, most major chip manufacturers have begun using a material called strained silicon, which is a more efficient electrical conductor than traditional silicon. Intel has said it will use low-k dielectrics and strained silicon in its quest for 45-nanometer chips, but will shy away from immersion lithography, citing uncertainties with the process.

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