At a technical conference this week, IBM gave some details of its upcoming Power6 chip architecture for servers. It's a 65-nm processor that operates in excess of 4-GHz.
SAN FRANCISCO At the International Solid-State Circuits Conference (ISSCC) here, IBM Corp. tipped its next-generation Power6 processor architecture for servers.
In various papers at the event, IBM indicated that the Power6 is a 65-nm processor that operates in excess of 4-GHz. Built around silicon-on-insulator (SOI) and other technologies, the Power6 is the follow-on processor to the company’s current Power5 architecture.
In one paper, the company described a 5.6-GHz Power6 processor with 64-Kb of Level 1 data cache. The processor is said to have an eight-way, set-associative design with a two-stage pipeline supporting two independent reads or one writes per cycle.
IBM also makes use of a 5-GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 microns wide and 1.2 microns thick.
In another paper, IBM described low-latency fixed-point and binary floating-point units for the Power6. The floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cyle, 13-FO4 pipeline,” according to the company’s paper.
The Power6 design uses dual power supplies, a logic supply in the 0.9-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
5 Top Federal Initiatives For 2015As InformationWeek Government readers were busy firming up their fiscal year 2015 budgets, we asked them to rate more than 30 IT initiatives in terms of importance and current leadership focus. No surprise, among more than 30 options, security is No. 1. After that, things get less predictable.
Join us for a roundup of the top stories on InformationWeek.com for the week of December 14, 2014. Be here for the show and for the incredible Friday Afternoon Conversation that runs beside the program.