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3/6/2006
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Intel CTO Tips 'Tera-Scale' Computing

Intel Corp. has disclosed details about its internal "tera-scale" research program that promises to usher in the next wave of computing.

SAN FRANCISCO — Intel Corp. on Monday (March 6) disclosed details about its internal “tera-scale” research program that promises to usher in the next wave of computing.

The Tera-Scale Computing Research Program involves more than 80 R&D projects at Intel. One of the goals in the program is to develop processors with tens — or even hundreds — of individual cores.

“This is a very significant challenge,” said Justin Rattner, Intel Senior Fellow and chief technology officer for the microprocessor giant, in a presentation. “The challenge is how do you feed the beast.”

Another pressing issue is power consumption. “We’ve been fanatic about energy efficiency,” Rattner said.

Besides power consumption, the development of programmable cores and interconnects are among the key enablers and challenges for these new multi-core processors, he said.

He also discussed the use of several other enabling technologies to develop these new processors, including transactional memory. “Transactional memory is a technique for coordinating how multiple threads access the same memory,” according to Intel.

Other enabling technologies include “configurable caches” as well as “scalable fabrics” for interconnects in multi-core processor designs.

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