Intel To Unveil 'Sliverthorne' Processor At Heart Of Ultramobile PCs
The lowest-power X86 chip to date will make its appearance at the International Solid-State Circuits Conference in San Francisco this week.
Intel Corp. will unveil the world's biggest commercial microprocessor as well as its smallest and lowest-power X86 chip to date at the International Solid-State Circuits Conference in San Francisco this week. But a server chip from Sun Microsystems and a cell-phone processor from Texas Instruments debuting at ISSCC will outflank Intel on both fronts.
Hoping to enable a new class of PC-compatible handheld devices, Intel will describe Silverthorne, a full X86 CPU that can handle active work at power consumption levels as low as 600 milliwatts. The device will eventually hit 2-GHz clock rates at its maximum 2-watt dissipation, thanks in part to Intel's latest 45-nanometer process technology.
Based on a new core, Silverthorne will deliver peak performance similar to the Pentium M (aka Banias) that powered the first-generation Intel Centrino notebooks.
"What has a lot of OEMs excited is the dynamic range of this processor," said Justin Rattner, chief technology officer of Intel. "It can be active at less than 1 W, but when it has a workload in front of it--like interpreting some Java byte codes to render a Web page--it can really crank."
Intel tried to reduce power consumption to 2 W on its existing Merom notebook core--a three-issue speculative pipeline--but "found it wasn't feasible," Rattner said. A research project dubbed Snowcone plowed a different path, which the Austin-based Silverthorne team eventually adopted.
"We became convinced that a simpler [in-order] two-issue core more reminiscent of the Pentium was the best approach to get to sub-1-W power consumption," Rattner said.
The 25-mm2 chip uses a host of power management techniques, including the ability to switch in or out of a new C6 deep-sleep state in just 100 microseconds. Intel redesigned its register files and cache circuits for lower active and standby power, created new I/O power planes and enabled the chip's 533-Mtransfer/second front-side bus with an optional energy-efficient CMOS mode.
While Silverthorne makes strides ratcheting down the power of an X86 processor, it is still a long way from integrated cellular chips that aim to deliver PC-like functions to pocket-size communicators. For instance, at the same ISSCC session, Texas Instruments will describe a cellular chip capable of decoding MPEG-4 video streams that includes an 840-MHz ARM11 to run applications, a 480-MHz TI C55x DSP core to handle 2G and 3Gbaseband comms, and a 240-MHz image processor.
The chip, a custom design for a cell phone maker expected to ship it in handsets this year, consumes 500 mW peak and for some cell phone apps as little as 100 to 250 mW. In deep-sleep mode, it dissipates microwatt range.
"It's all about power in this market, where we are designing systems based on 22-gram batteries," said Jeff Bellay, vice president of wireless advanced technology at TI.
To reduce power, TI used independent power domains, dynamic frequency and voltage scaling, adaptive voltage scaling and split-rail SRAMs and ROMs. The chip is believed to be the first 45-nm cellular processor TI has publicly described and the first to crank an ARM11 processor to 840 MHz.
By contrast, Silverthorne is part of a broader group of five or more chips--including Wi-Fi and ultimately WiMax silicon--that Intel will gather into designs for so-called ultramobile PCs and mobile Internet devices.
"The competition considers 2 watts laughable," said Will Strauss, principal of Forward Concepts (Tempe, Ariz.), referring to Silverthorne's maximum dissipation. "Six hundred milliwatts is the power budget for an entire cell phone processor and baseband."
Intel is not aiming Silverthorne at smart phones, however, but at a class of devices somewhat bigger and more powerful, potentially running full Windows Vista software loads.
"Silverthorne probably won't appear in anything much smaller than a paperback book," said Nathan Brookwood, principal of market watcher Insight64 (Saratoga, Calif.). But a follow-on design with lower power consumption in 2009 "could very well appear in smart phones," he said.
Whether the new systems that Intel has roughly described as ultramobile PCs and mobile Internet devices take root remains to be seen. Analysts expect the market for smart phones--of which the ARM-based Apple iPhone is now the poster child--to grow from fewer than 100 million units this year to more than 400 million units by the end of 2010.
"It's not clear if Windows makes it down into this [ultramobile] form factor successfully," said Brookwood. "The initial ultramobile PCs from Samsung and OQO have not set the world on fire."
Qualcomm also aims to enable very powerful yet mobile systems with its pending Snapdragon architecture, believed to be based on a modified version of the ARM Cortex core.
"All these companies are targeting the ultramobile device," said Strauss.
Sun, Intel in server fray In computer servers, Intel will roll out a four-core version of its Itanium server CPU that packs a whopping 2.05 billion transistors--more than have ever been used in a commercial microprocessor, according to the ISSCC organizers. Tukwilla measures in at nearly 700 mm2 and consumes an equally hefty 170 W.
Intel claims that a 130-W version of the chip will double the performance of its current dual-core Itanium. Tukwilla marks Intel's move into server chips that integrate a memory controller and high-performance interconnect similar to the Opteron server CPUs of archrival Advanced Micro Devices.
Tukwilla runs at up to 2 GHz, packs 30 Mbytes of cache and is the first Intel CPU to support the company's new QuickPath processor interconnect, which competes with AMD's HyperTransport. QuickPath is slated to appear on several Xeon server processors starting late this year.
Sun Microsystems will outshine Tukwilla with the disclosure of its long-awaited Rock processor, a 16-core chip running at up to 2.3 GHz that breaks fresh ground in a number of areas. Rock is the first CPU to implement scout threads and transactional memory--two features expected to become increasingly important for multicore microprocessors.
Each of Rock's 16 cores supports two simultaneous computing threads. In addition, each core supports up to two scout threads that can not only pre-fetch and execute but retire instructions in an out-of-order fashion without using traditional, complex out-of-order memory structures, said Marc Tremblay, chief technology officer of Sun's microelectronics group.
Hardware support for the scout threads required only about 5 percent of the nearly 400-mm2 die, in part because the cores were already multithreaded. "We effectively added 3-D structures where you can essentially hide bits under wires of a multiported register file," Tremblay said.
With similarly small hardware additions, Rock supports so-called atomic transactions. By tagging groups of instructions to execute at essentially the same time, the technique reduces the complexity and inefficiency of current locking mechanisms used to synchronize operations, especially in large database software.
Computer scientists have long seen the feature as one of the initial planks of a new parallel programming model that will be needed for multicore architectures. As the first to implement it, however, Sun risks being ahead of broad industry support.
Tremblay said the syncing mechanism in widely used Java code maps well to the new Rock instructions, and Sun's Solaris operating system and thread libraries will support atomic transactions so users can get immediate benefits. As for third-party databases and other applications, he said, "I believe we will have ISVs support this the day we ship systems."
Sun is working to create a consortium that would define an application programming interface for its implementation of atomic transactions and make the API available as open-source software. At least two large computer user organizations are backing the move.
Sun is also developing a simulator for its approach that will be released as open-source software. It is still possible, however, that competitors such as IBM, Intel and Microsoft could be motivated to define a competing standard before Rock-based systems ship.
One other novel feature in Rock is an approach to linking multiple CPUs in a system via direct memory connections over a 2.67-Gbit/second interconnect. Tremblay would not say how the approach works or how many CPUs can be linked, but he did say, "There is no such thing as local CPU memory in our system."
One blemish on the Rock design is that it sports a peak power consumption of 250 W. "We decided what mattered was power efficiency [more than overall power], and it is an air-cooled processor" that uses no exotic thermal technologies, Tremblay said.
He would not share performance data for the processor but said it meets its targets of having the best multithreaded performance and "competitive" single-threaded performance.
A version 2.0 of the chip is expected to tape out in a few weeks, Tremblay added, and systems based on it could ramp within a year.
Without hard performance numbers, it is difficult to gauge how Rock will fare against server chips from IBM and Intel, said Brookwood.
Nevertheless, the analyst noted that "Rock is implementing features other people have only talked about. [Sun] can do that because they have a much simpler core" and their own operating system.
Overall, Brookwood added, "Sun has gotten a lot further, in less time, with the concept of thread parallelism it defined in 2002 than Intel has with the instruction parallelism it defined in the early 1990s for Itanium."
The Business of Going DigitalDigital business isn't about changing code; it's about changing what legacy sales, distribution, customer service, and product groups do in the new digital age. It's about bringing big data analytics, mobile, social, marketing automation, cloud computing, and the app economy together to launch new products and services. We're seeing new titles in this digital revolution, new responsibilities, new business models, and major shifts in technology spending.