When it comes to chips, Intel believes in the old cliché that you can't be too thin. The world's leading chipmaker is pushing the semiconductor manufacturing envelope by shrinking the size of the circuits that conduct electricity in chips from 90 nanometers to 65.

"With this advanced technology, circuit designers can add more circuit features and increase performance, while staying within power limits," says Mark Bohr, Intel's senior fellow and director of process architecture and integration.

Intel's 65-nanometer capability has already been demonstrated in production of functional 70-Mbit static RAM devices with more than a half billion transistors, Bohr says. The 65-nanometer chips are on track to be shipped in 2005, he says.

The new generation of product will include enhancement to Intel's strained-silicon technology, which was introduced two years ago as part of the 90-nanometer-generation process. The technology stretches electron grid patterns, letting them flow faster and with less resistance. It also lets the silicon atoms switch faster.

While there are always issues arising in qualifying new processes for production, Bohr says that the move to 65 nanometer should be easier than the move from 130 nanometer to 90 because many of the chipmaking technologies introduced at the 90-nanometer level have already been proven in production.

By using strained technology in a 65-nanometer process, transistor drive current can be increased by 10% to 15%. At 65 nanometers, the transistors will have much less leakage than previously, improving power usage, he says. In addition, chip power consumption can be reduced by 20%.

Nathan Brookwood, an analyst with Insight 64, says the announcement demonstrates that Moore's Law, which says transistor density will double every two years, "is alive and well." Also, the new features affecting power dissipation show "Intel has gotten the message that they need to address the power of these chips and the heat they are dissipating, which directly impacts end users," he says.

Overall, by moving to a 65-nanometer process, Intel will be able to cut the chip size of existing designs in half, reducing cost and power usage, Bohr says. By keeping the chip the same size, Intel could double the number of transistors in a given die area, allowing for the introduction of new circuit capabilities and improved performance.