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Intel's Bounding Ahead With Chip Designs


Intel is trying to quickly improve its 64-bit Itanium products, applying its successful market strategy for 32-bit chips.

By Aaron Ricadela
InformationWeek
January 16, 2003 12:00 AM

Intel's production plans call for an Itanium 2 chip next year that triples the amount of cache compared with its current processors and a dual-core processor by 2005, a generation of technology earlier than expected.

The planned introductions of an Itanium 2 chip based on Intel's "Madison" design with 9 Mbytes of Level 3 cache and of dual-core technology in the company's "Montecito" generation of chips could give Intel a boost as it seeks to displace RISC chips from IBM and Sun Microsystems in servers handling business workloads.

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"Send a nice bonus check to the people doing their process technology," says Jonathan Eunice, an analyst at researcher Illuminata. "It means Intel as a company has more confidence it will be able to march more rapidly along in getting a hugely complicated chip shrunk down in a very tight time frame."

Intel is trying to quickly improve its 64-bit Itanium products, applying its successful market strategy for 32-bit chips. Itanium 2, introduced last year, outperforms RISC processors on a closely watched integer processing benchmark and is second only to Hewlett-Packard's Alpha processor for running floating-point jobs. Now, Intel wants to prove that Itanium chips, aimed at the largest computing jobs, can outperform competitors on benchmarks that measure business tasks such as database transaction processing and Web-page serving, says Jason Waxman, a marketing manager for Intel's enterprise processors. "We're more interested in [the Transaction Processing Performance Council benchmark] on Oracle and SQL Server," he says.

Intel's next Itanium 2 product, code-named Madison, is on schedule to ship this summer, the company says. Madison chips will run at 1.5 GHz, compared with a top speed of 1 GHz for today's Itanium chips, and contain 6 Mbytes of Level 3 cache--which helps shuttle data through computers faster--compared with 3 Mbytes. Intel plans next year to ship a second Madison chip that contains 9 Mbytes of Level 3 cache and runs at a top speed of more than 1.5 GHz.

Madison chips also use a 0.13-micron manufacturing process, which can increase the number of transistors on a chip compared with today's 0.18-micron process. "The number of transistors is growing very rapidly," Eunice says. "The question for designers is what you do with them. Intel has decided on big caches. It can have a very dramatic impact on application and database benchmarks."

In 2005, Intel plans to deliver a processor code-named Montecito, which uses a 0.09-micron manufacturing process. Montecito chips will be the first to contain two processing cores on a single silicon die. Previously, the company had said its next generation of chips after Montecito would be the first to use the dual-core technology.

Tuesday, Intel reported that fourth-quarter net income doubled, but said revenue in the current quarter will likely decline a bit. Intel also said it plans to reduce spending on new plants and production equipment after a spending boom in recent years.


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