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Overview: This research paper by KTH - Royal Institute of Technology presents an analysis of a frequency detector used in a synthesizer application. The discrimination is analyzed in the presence of timing errors like offsets and jitter. Due to the nature of the detection process, small DC shifts in the output frequency can be identified. Jitter accumulation is greatly reduced since the loop is effectively opened after half a reference period. A linear model for steady state operation of the synthesizer is derived and simulated. The simulated output spectrum is shown for a IEEE 802.11b application.
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