LONDON IBM Corp. scientists have devised a way to create vacuum spaces between copper wires in semiconductors and claimed the technique -- which borrows from nature -- will lead to chips that consume less power and run faster.
IBM said Thursday (May 3) its self-assembly nanotechnology process can be incorporated into standard CMOS manufacturing lines without disrupting operations or retooling.
Intial results at IBM labs indicate that the electrical signals on chips can flow 35 percent faster, or the chips can consume 15 percent less energy compared to the most advanced chips made using conventional techniques.
IBM researchers claim this is the first demonstration of the ability to synthesize mass quantities of self-assembled polymers and integrate them into an existing manufacturing process while achieving improved yields.
IBM plans to introduce the technology into the 32-nm manufacturing process being readied at its East Fishkill, N.Y., fab that is expected to come online in 2009. Initially, it would be used for devices made for IBM's server products and later for IBM chips made for outside customers.
"By moving self-assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow," said Dan Edelstein, IBM fellow and chief scientist of the self-assembly airgap project.
While performance and power-saving improvements are "evolutionary", Edelstain said chip design and manufacturing are "revolutionary."
He added that the patented self-assembly process moves IBM's nanotechnology manufacturing method that had shown promise in laboratories into a commercial manufacturing environment for the first time. IBM claims it will provide the equivalent of two generations of Moore's Law wiring performance improvements in a single step, using conventional manufacturing processes.
The technique creates a vacuum between copper wires on a chip, allowing electrical signals to flow faster while consuming less power. The self-assembly process enables the nanoscale patterning required to form the gaps, and this patterning is considerably smaller than current lithographic techniques can achieve.
The IBM researchers said a vacuum is the ultimate insulator for wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip.
The process was jointly invented between IBM's Almaden Research Center (San Jose, Calif.) and the Thomas .J. Watson Research Center (Yorktown Heights, N.Y.) The technique was perfected for future commercial production at the College of Nanoscale Science and Engineering of the University at Albany. The lab also operates as part of the Albany NanoTech facilities, which has close ties to IBM. IBM's Semiconductor Research and Development Center in East Fishkill, also contributed.
IBM said a key advance in that its technology skips the masking and light-etching process. Instead, it uses the right mix of compounds, which are poured on to a silicon wafer with the wired chip patterns and then baked.
The process provides the proper environment for compounds to assemble in a directed manner, creating uniform, nanoscale holes across an entire 300-mm wafer. The holes are just 20-nm in diameter, and are said to be up to five times smaller than are typical with current lithography techniques.
Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires.
The IBM researchers noted that the self-assembly process is used in nature to create seashells, snowflakes and even tooth enamel.