Chip Design Gets New Slant

Chip manufacturers have been trying to break or at least bend the law for many years now-Moore's Law, that is. Intel co-founder Gordon Moore observed in a 1965 speech that new iterations of semi-conductors contain roughly twice the capacity of their predecessors, and that new iterations are typically released 18 to 24 months after the previous versions. Since that pronouncement, chip manufacturers have tried to figure out innovative ways to match or exceed that pace.

One of the latest twists is a chip design that Simplex Solutions Inc. developed with partner Toshiba Corp., called the X Architecture. This approach lets interconnects among transistors on a chip branch off diagonally in any of eight directions to reduce the wiring on a chip by more than 20%. According to Simplex, this wire-length reduction will provide an improvement in chip performance of more than 10% while requiring 20% less power-and will do this without any changes to existing cell libraries, memory cells, compilers, and IP cores.

Current chip designs use the Manhattan architecture, which has right-angle interconnects. In a five-layer metal chip design, the X Architecture leaves layers one through three alone while rotating the direction of the interconnects in layers four and five by 45 degrees.

Simplex and Toshiba have been working on the X Architecture project for two years. So far, they've completed a RISC processor design that uses the X Architecture. Additional designs are expected next year. It seems likely that much of the initial use of the technology will be for custom-designed chips.

Several leading semiconductor companies recently formed a consortium to speed up the adoption of the X Architecture, provide a source for education, and facilitate support and fabrication. The group has undertaken a five-year initiative to implement changes in manufacturing necessary to take advantage of the X Architecture.