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Gartner Analyst Gives ASIC, FPGA Chip Markets Thumbs Up

Both the application-specific integrated circuit and field-programmable gate array markets are in good health and will help drive overall semiconductor growth this year, the analyst says.
ANAHEIM, Calif. — The application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) markets are in good health, according to Bryan Lewis, vice president and chief semiconductor analyst for Gartner Dataquest.

Speaking to an audience of mostly EDA executives on the eve of the Design Automation Conference (DAC) Sunday (June 12), Lewis detailed the results of an ASIC and FPGA market "physical exam," which both passed.

Lewis said the overall semiconductor market outlook for 2005 has improved. He is now predicting 5.9 percent growth for the market in 2005, higher the 5 percent his firm had previously predicted, and growth of 6.5 percent for 2006.

Lewis said that growth for memory ICs would be flat in 2005 and 2006. He said the overall market's growth would be driven by ASIC and FPGA growth.

Lewis said the ASIC market grew by 11 percent in 2004, lower than the overall semiconductor industry's 21 percent growth, but still a healthy figure. He said the ASIC market would grow by 3.9 percent in 2005 and then outpace the overall industry's growth in 2006 by posting 8.3 percent growth.

Lewis said the up-tick in 2006 ASIC growth would be driven by the introduction of new video gaming systems, notably Sony Corp.'s Playstation 3. He said that video gaming systems are the largest driver of the ASIC market.

"A lot of people think that the FPGA market has taken over the ASIC market," Lewis said. "That's not true. The ASIC market is far from a dead market."

The next two years will also be strong years for FPGAs, Lewis said. He forecast FPGA growth of 5.8 percent for 2005 and 13.4 percent for 2006.

Lewis said the number of FPGA design starts dwarfs the number of ASIC design starts and forecast that the number of FPGA design starts would grow from just over 80,000 in 2005 to more than 110,000 by 2010. But, he said, EDA tool vendors still rightly concentrate more heavily on the ASIC market because ASIC revenue is significantly higher.

"ASICs are clearly where the revenue is, but you can't ignore the FPGA market," Lewis said.

Commenting on the migration to 90- and 65-nanometer design rules, Lewis cited the results of a Garter Dataquest (San Jose, Calif.) study that found that nearly 20 percent of designs in the Americas region are now being done at 90-nm. He forecast that 65-nm designs would make up 6.5 percent of all designs in 2005 and 16.4 percent in 2006.

Lewis said that 65-nm adoption would likely be slow and dominated by big companies with big resources who are willing to spend money to migrate to smaller linewidths.

"Fewer people want to get on that [65-nm] bandwagon and push the technology," Lewis said. "People want to push 130 nm as far as they can."

Lewis predicted "big growth" over the next few years for structured, or "platform" ASICs, devices in which more than half the chip is predetermined and preverified using embedded intellectual property. But, he noted, while structured/platform ASICs now represent one-third of all designs, they still make up less than 10 percent of ASIC revenue.

Lewis forecast year-over-year growth for the overall semiconductor industry through 2008. By 2009, he said, overcapacity would become a problem and the industry would slip into a downturn.

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