The company is scrapping the Reidland platform and Whitefield processor that had been on its Xeon processor roadmap for multiple-processor systems for 2007. In its place, Intel will offer what it says will be a higher-performing Caneland platform with Tigerton processor. The associated, and as yet unnamed, chipset will use a dedicated high-speed interconnect to move information on and off the processor instead of the traditional front-side bus.
Although details of the new interconnect were not fully disclosed, the technology appears similar to the direct-connection architecture used by AMD in its processors in lieu of a front-side bus. Analysts had speculated that Intel would begin moving away from its use of a front side bus in 2007 or 2008 timeframe.
The use of a dedicated high-interconnect system would be particularly appealing in multiple-processor systems, where the various processors would have to compete for use of the front-side bus. Although the new interconnect is expected to make its way onto other Intel processors, a spokesman said there is currently no available roadmap or time table.
The changes will not affect the current Xeon dual-processor product line, or the Xeon MP product line for 2006.
Intel also disclosed that is scaling back its plans for its next-generation Itanium processor, called Montecito. Originally scheduled for early 2006, the processor is being delayed until mid-2006 while Intel completes additional work to ensure it is ability to hit its quality specifications, the spokesman said. In addition, the Montecito will not incorporate the previously disclosed Foxton technology, which would allow the chip to automatically control clock speed and associated heat dissipation.
Also, the Montecito will come with either a 400- or 533-megahertz front-side bus, but not with a 667-megahertz option as had been previously indicated. The top-end clock speed for the Itanium has been reduced from 2 gigahertz to 1.6 gigahertz.
The delay in volume production of the Montecito will also have the trickle-down effect of delaying the next two generations of Itanium currently on the Intel roadmap.