The companies say the "dual stress liner" technology is a second-generation strained silicon process that will be integrated into their manufacturing flows without impacting yields and without the needed for additional "exotic" materials.
As it has become more difficult to incorporate traditional physical shrinks of transistors without increasing power budgets in processors, silicon manufacturers have turned to strained silicon technologies to boost performance, says Nick Kepler, VP of logic technology development at AMD.
"The basic approach involves modifying the electrical properties of the transistor such that the electrical current flows more easily," he says.
Traditional silicon structures have two types of transistors: N channel and P channel. By placing a physical "strain" on the transistor channels, performance can be increased. Two types of strain that can be placed on the channels are tensile and compressive.
While N channel transistors can achieve superior performance when placed in a tensile strain, P channel transistors are degraded. Conversely, P channel transistors show a performance boost when placed in a compressive strain, but degrade with a tensile strain.
"The key is to place the right type of strain on the right transistor," says Lisa Su, VP of technology development and alliances at IBM.
The dual stress linear technology allows each channel to be simultaneously strained by the optimal process, providing the 24% performance boost, or allowing for a reduction in power at the same performance level, she says.
The AMD-IBM strained silicon technology differs from that used by Intel, which uses an embedded silicon germanium material on the transistors, Kepler says.
"We have looked at silicon germanium, but that involves adding an additional material and using a more involved process technology," he says.
A spokeswoman for Intel says the company has shipped more than 60 million microprocessors since it introduced its strained silicon technology in 2003 and hasn't experienced manufacturing problems associated with technology.
Intel plans to introduce its second-generation strained silicon technology in conjunction with its use of 65-nanometer process technology, which the company expects will boost overall performance by up to 15%, the spokeswoman says.
AMD says it will use dual stress linear technology on AMD64 processors beginning in the first half of 2005, including dual-core processors. IBM plans to use the technology on multiple processor platforms beginning in early 2005, including its Power architecture-based chips.
The dual stress linear technology was developed by researchers at IBM's facility in East Fishkill, N.Y., and AMD's facility in Dresden, Germany.