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AMD Opens Bangalore R&D Center

When you get CEO Hector Ruiz to fly into India to open up a new engineering facility, you know AMD is getting serious about 45nm quad-core chips.
When you get CEO Hector Ruiz to fly into India to open up a new engineering facility, you know AMD is getting serious about 45nm quad-core chips.The chipmaker is doing a little ribbon cutting this week on a new 52,000 square-foot center for engineers, administration, sales, and marketing. The goal is to design, test, and help spread the message of "Shanghai," AMD's first 45nm quad-core microprocessor. It's the next in line of quad-core AMD Opteron microprocessors. The first was previously codenamed "Barcelona."

Shanghai is expected to be released in the first quarter of 2008. Designed for AMD's 22x and 82x sales family, the chip is expected to feature Hyper Transport 3 support.

AMD's test facility to India is part of its growth plan in Asia. Back in August, AMD senior VP Rick Hegberg told LiveMint.com that India and China are the firm's topmost priorities.

"We have a market share in the mid-20% range in our global business and we see no reason, why in the next three quarters our India business cannot acquire that same share," Hegberg told reporter Regina Anthony.

Ruiz on Thursday backed up the sentiment:

"In AMD's quest to become the technology partner of choice for the industry, this facility is vital to help us design and deliver industry-leading solutions specifically tailored to the needs of our customers in India, and for all our customers worldwide," he said.

AMD will also need Bangalore to help it keep competitive with Intel's 45 nm roadmap. The two chipmakers are already on track to release desktop quad-core processors before Christmas. However, AMD will be selling 65-nm Phenom chips while Intel will be selling its first 45-nm Penryn parts.

While the process technology -- 65 nm vs. 45 nm -- won't mean too much in the short term for desktops, it will make a world of difference in servers, especially as AMD and Intel improve on their chipset designs to help support hypervisor/virtualization technology; power optimization; and security.