Chip technology from Intel and Micron combines the best qualities of DRAM and solid state memory. It may lead to big changes in mobile and data center operations.
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Micron and Intel have produced memory chips based on a new three-dimensional cross-point technology that will improve the density of memory for close-to-the-CPU processing, such as in-memory database operation. It improves on the speed of the typical solid state device.
Brian Shirley, Micron's VP of memory technology and solutions, said in an interview that NAND -- or non-volatile solid state drives -- have achieved great memory densities, but the data on them must be accessed in blocks, a slower process than being available over a random-access bus.
Likewise, the volatile DRAM used for internal server memory has achieved great speed of access, but has been limited in the amount of capacity it can provide on a single chip. Intel and Micron's 3D XPoint technology moves away from a memory chip architecture based on transistors, and combines speed of access with three-dimensional memory circuits yielding high density. Like NAND, 3D XPoint is non-volatile, with data remaining in place after the power is shut off.
3D XPoint is 1,000 times faster than the non-volatile memory found in solid state devices, and 10 times as dense as DRAM memory occupying the same amount of space, the two chip makers claimed in a statement on Tuesday. "It fills the gap. It combines the best of both DRAM and NAND solid state aspects," Shirley said from his office in Boise, Idaho.
Shirley acknowledged that memory breakthrough announcements are made each year, often representing merely theoretical advances or achievements in a lab that may never be mass produced in the factory. "There are a lot of PowerPoint presentations out there," Shirley conceded. But, he added, "Intel and Micron are talking about a technology that is in a production fab right now."
3D XPoint chip dies.
The two firms are manufacturing their first 3D XPoint chips in a Micron NAND fabrication plant in Lehigh, Idaho. XPoint memory products will be available from the two firms in 2016, Shirley said. If so, then they are likely to usher in a new era of more powerful database servers, big data analytics applications, and mobile devices.
Shirley said the chips' design gets away from transistor-based memory, and substitutes "interleaved rows of memory lines [circuits] that makes use of "a new combination of materials" that Intel and Micron declined to define in detail. "The net is a simple structure which we can manufacture, and which enables the high-memory density," sais Shirley. "And the exciting thing is that it has quite a bit of scalability still in front of it."
Manufacturers have found it increasingly difficult to shrink memory circuits and pack memory cells with sufficient electrons to produce highly reliable memory chip function. The 3D XPoint approach claims to do just that, with a series of scalability improvements still to come.
Asked to illustrate the speed of data access allowed by the technology, Shirley said the industry's top performance comes from DRAM chips, which allow data access within tens of nanoseconds (billionths of a second). The non-volatile NAND solid state chips provide data access at speeds that measure in the hundreds of microseconds or 100,000s of nanoseconds. The 3D XPoint technology provides data access in hundreds of nanoseconds.
Asked to explain the potential memory capacity of the new technology, Shirley said DRAM chips can be fabricated in 1 GB capacities. NAND chips can be fabricated with 48 GB capacities. The 3D XPoint chips will initially be fabricated in 16 GB capacities, with larger chips to follow in successive generations, he said.
"Part of the magic of this technology is that the memory cells and memory arrays use very simple structures. They don't rely on transistors," said Shirley. Both Intel and Micron expect them to be manufacturable on a reliable, high-yield basis. They're using what is currently a NAND wafer plant in Lehigh for their pilot production line.
According to Shirley, the size of the memory cells can continue to shrink on the chips, in part, because it is "not a charge-based data storage approach. We are actually changing the atoms in the memory cell" as the basis for data retention without charge.
"It's a different mechanism. It gives us the high densities with the higher speeds as well," he said.
Charles Babcock is an editor-at-large for InformationWeek and author of Management Strategies for the Cloud Revolution, a McGraw-Hill book. He is the former editor-in-chief of Digital News, former software editor of Computerworld and former technology editor of Interactive ... View Full Bio
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