AMD Plans Updated Server Platform Next Year

The chipmaker also plans to release its first 45-nanometer processor, code-named Shanghai, by the end of the year.
Advanced Micro Devices plans to release in the first half of next year a server platform that will be based on a new chipset.

In addition, the chipmaker plans to release 45-nanometer processors for servers and desktops that will be rolled out in the fourth quarter of this year and first quarter of 2009.

AMD announced its plans as rival Intel prepares for its Developer Forum that starts Tuesday and runs through Thursday in San Francisco. An AMD spokesman said full details of the server chipset would be released next week.

Meanwhile, AMD plans to release its first 45-nanometer processor, code-named Shanghai, in the fourth quarter. Shanghai is AMD's response to Intel's Nehalem microarchitecture. The first Nehalem chip, called the Core i7, will be a quad-core processor for high-end desktops and two-socket servers.

Shanghai will be AMD's first 45-nm processor. The number refers to the size of transistors on a chip. By shrinking the size from current 65-nm transistors to 45 nm, AMD will be able to get more of the components on a piece of silicon, thereby increasing performance without increasing power consumption.

Shanghai will be a four-core processor that delivers 25% better performance than the company's current 65-nm quad-core Opteron, formerly known as Barcelona. Shanghai also will ship under the Opteron brand.

Intel is ahead of AMD in implementing the manufacturing process necessary for building 45-nm processors, which Intel started shipping in the fourth quarter of last year. Intel has transitioned most of its product line to 45 nm.

The Core i7 is scheduled to ship in the fourth quarter, along with a server version for two-socket machines. Nehalem-based mobile and mainstream desktop chips, along with chips for servers with more than two sockets, are set to ship next year.

Nehalem, based on Intel's 45-nm manufacturing process, is able to scale from two cores to as many as eight. Each core will have two software threads.

Editor's Choice
James M. Connolly, Contributing Editor and Writer
Carrie Pallardy, Contributing Reporter
Shane Snider, Senior Writer, InformationWeek
Sara Peters, Editor-in-Chief, InformationWeek / Network Computing
Brandon Taylor, Digital Editorial Program Manager
Jessica Davis, Senior Editor
John Edwards, Technology Journalist & Author