Unfortunately, shortly after these parts launched -- Barcelona in September and Phenom shortly before the end of 2007 -- a translation-lookaside buffer bug reared its head. This turned out to be more a public-relations black eye for AMD than anything else. I don't want to say that erratum aren't important, but this particular glitch doesn't have a significant effect on the desktop.
On the server side, the TLB glitch clearly caused lots of consternation. However, much of the to-do was stuff like people discussing just how much of a performance hit Barcelona took if you implemented the workaround AMD issued.
Interestingly, my discussions with system builders indicate that the bug may actually have gotten conflated with other issues. Namely, all new architectures take time getting used to, and it's possible that some of the stuff surrounding Barcelona in the past few months involved engineers understanding the fine points of the chip's timing issues.
Regardless, what's clear now is that AMD is about to put this issue behind it, and launch full-bore into a quad-core server processor war with Intel and its Xeon line.
As Kevin Knox tells me on the video: "We are going to be shipping our Barcelona B3-stepping parts [which have the bug fix] at the end of this month, with shipments of systems for the public starting in April."
The B3 Barcelonas will be available in speed grades of up to 2.3-GHz (and 75-W power envelopes), with clock speeds of 2.5-GHz at 105-W coming in the second quarter.
In this video, Knox talks specifically about the new Barcelonas. I'll have a follow-on next week, where we discuss data-center issues, including power and cooling.
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