Inside AMD's Phenom And Opteron Quad-Core Architectures

When Phenom and Barcelona ship later this year, AMD is hoping the new 10h architecture it's using will help it do some performance leapfrogging of its own. The design incorporates a bunch of enhancements, including: new instructions, improved floating-point execution units, faster data transfer between floating-point and general-purpose registers, and 1-Gbyte paging, to name a few. The 10h architecture also incorporates optimization to make AMD's hardware-based virtualization run faster.

	(click image for larger view) This die shot identifies the different functional units of Barcelona, AMD's upcoming quad-core Opteron. view the image gallery

Beyond the computing power packed onto the chip itself, much of the elegance of the AMD approach is evident in the way it handles I/O to external devices as well as interprocessor communications. In contrast to the traditional method of sending outbound data over a frontside bus, AMD has long used its proprietary HyperTransfer interface. With10h, HyperTransport3 debuts. This next-generation upgrades boosts the total bandwidth of the link to 20.8 Gbytes/sec.

When AMD discussed its quad-core Opteron at the International Solid State Circuits Conference in February, it said the the processor contained 450 million transistors and would be fabricated in 65-nm CMOS technology. This puts AMD at something of a disadvantage vis--vis Intel, which will ship 45-nm quad core processors later this year. In terms of chip construction, smaller is better because its enables lower power operation. It also allows the chip vendor to get higher yields, by placing more processors on each of the large 300-mm wafers on which the chips are made before they're sliced off and individually packaged.

Intel's sheer size has long given it a big advantage in chip manufacturing. It's currently thought to be well ahead of AMD on the road to 45 nm. Intel said last week that it's in the process of bringing four factories on line to make 45-nm chips. However, for its part, AMD is also rushing to ready 45-nm and has reportedly already made prototype wafers at its Fab 36 in Dresden, Germany.

	(click image for larger view) Four Barcelonas are used in this multiprocessing configuration. view the image gallery

In terms of on-chip features, the four cores of Barcelona are expected to each have their own, 512-kB L2 cache, and to share a 2-MB L3 cache. The processor will support a fast, DDR2/DDR3 memory interface.

Interestingly, the race to four cores is also something of a race to eight cores. AMD is emphasizing that Phenom will support dual-socket motherboards. This will allow two chips, each with four processors, to be placed in the same system, for eight core overall. Barcelona will allow similar multi-socket configurations (including a four-socket NUMA design at the very high end), as will Intel's offerings.

Diving deeper into the laundry list of arcane technical improvements AMD has packed into the new 10h architecture, which will debut with Phenom and Barcelona, there are the following improvements:

Beefed up floating-point support. Earlier processors had 64-bit floating-point execution units. Because of 10h, AMD will be able to equip Phenom and Barcelona with 128-bit floating-point units, if it so chooses. The wider design will double the performance of floating-point vector operations.

Instruction-fetching improvements. The fetch window has been widened to 32 bytes from 16 bytes. This will allow the processor to handle a complete sequence of three large instructions per cycle.

Large page support. As mentioned earlier, the 10h processors now support 1-GB paging. The feature provides a big benefit to applications, such as multimedia, which operate on large data sets.

Instruction-set improvements. These include the addition of two advanced bit-manipulation instructions, which operate on general purpose registers

Virtual machine optimizations. The 10h architecture includes many improvements to boost the performance of AMD's virtualization technology, as well as compiler-related optimizations.