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Roger Smith
 
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Intel Nehalem Processors--The Next Generation

Before a standing-room-only session at the Intel Developer Forum on Tuesday in San Francisco, soft-spoken Intel Fellow Rajesh Kumar did a high-level walk-through of Intel's next-generation core microarchitecture (Nehalem) processors in a presentation titled "Screaming Performance, Efficient Power."

| Roger Smith | August 20, 2008 06:38 PM

Before a standing-room-only session at the Intel Developer Forum on Tuesday in San Francisco, soft-spoken Intel Fellow Rajesh Kumar did a high-level walk-through of Intel's next-generation core microarchitecture (Nehalem) processors in a presentation titled "Screaming Performance, Efficient Power."Kumar, who led the development of the circuits and low-power technology in the Nehalem processors, talked at length about key ingredients responsible for performance and energy efficiency in Nehalem. These include:

  • QuickPath, a data transfer technology that integrates a memory controller into each microprocessor, and connects processors and other components with a new high-speed interconnect.

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  • Hyperthreading technology, which will allow each core within a Nehalem processor to appear as a pair of virtual cores. This allows better utilization of the pipeline built into each core.

  • Turbo Mode technology, which improves power efficiency of the chips by disabling inactive cores to prevent power leakage. Turbo mode allows the running cores to utilize more power when other cores are off or in low power modes.

  • A new circuit/process technology called Power Gate that can shut off both switching power when idle and leakage power. "The key idea in power management is quite simple -- to shut things off when not in use," Kumar said. He explained that when one or more of the cores on a Nehalem chip is powered down, the processor can divert extra power to the cores that are in use by increasing their clock speed and voltage -- thus giving the active cores extra performance headroom.

  • Nehalem also uses low-power, slower static CMOS transistor chip design rather than faster but more power-hungry designs that have been used in previous Intel designs, such as low-voltage swing in the Pentium 4 chip.

    Highlighting the guiding principles behind Nehalem, its microarchitecture, cache organization, instruction set enhancements, and innovative power management, Kumar summarized that Nehalem fulfills the 45-nanometer "tock" of Intel's "tick-tock" strategy, which aims to shrink processor size with a new manufacturing process in odd years, and roll out new processor architectures in even years.

    Kumar's presentation was generally well-received by the capacity crowd, one of whom, Bill Heckel, a principal performance engineer with travel technology company Sabre, admitted to being impressed by the "continual increase in available CPU power driven by Intel's relentless efforts."

    For more, see:

    Antone Gonsalves' InformationWeek article "Intel Road Map Stretches From Quad Cores To Mobile Internet"


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