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R. Colin Johnson
June 24, 2014
1 Min Read
Intel unveiled its many-integrated core (MIC) roadmap to expand the high-performance computer market at the International Supercomputer Conference (ISC-14) in Leipzig, Germany, June 22-26. The multi-faceted unveiling revealed the details of a new version of its massively parallel processor -- the Xeon Phi -- as well as a new interconnection fabric based on Intel's silicon photonics advances, and an educational program designed to give every new programmer on the planet the opportunity to learn how to code for parallel processors.
"In just 16 years, we've seen the fastest supercomputer in the world at 3 teraflops migrate down to a single socket," Charles Wuischpard, VP and general manager of Intel Workstations and High Performance Computing Data Center Group, told EE Times in a conference call.
Intel has been talking about a new version of its massively parallel Xeon Phi processor -- currently with 60 cores per chip -- but at ISC-14 unveiled many more, but not all, of the details about the new chips, which will be available in the second half of 2015. Its current-generation Xeon Phi is a 1-teraflop chip cast in 22 nanometer CMOS and sold on a PCIe board in several versions. The Green500 list pronounced it the most power-efficient parallel processor in the world. The Top500 supercomputer list just announced the Xeon Phi powered Tianhe-2 (Milky Way 2) supercomputer at the National Supercomputing Center in Guangzhou, China, as the fastest in the world for the third time running.
Read the rest of this story on EE Times.
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