Are Chips Getting Too Hot To Compute?

SAN FRANCISCO — Contrary to popular belief, the impact of high temperature on a chip design is not among the most immediate concerns for advanced IC design, according to Robert Pitts, senior member of the technical staff and 45-nanometer platform manager at Texas Instruments Inc.

Participating in a panel discussion on IC thermal issues here at the Design Automation Conference Tuesday (July 25), Pitts acknowledged that he is concerned about thermal impact at the "mid-45- and 32-nm" nodes, but that it is currently "not our No. 1 problem." Right now, "thermal is a second-order priority," Pitts said. Dynamic IR drop, he said, is chief among more immediate concerns.

But thermal gradient does remain a long-term concern. "Several trends are going in the wrong direction," Pitts said. "They have been going in the wrong direction for several technology nodes."

Among these trends are increasing chip power density and feature integration, Pitts said, as well as packaging options that further increase power density, such as stacked die and system-in-package modules.

Focus on thermal issues in IC design may be ahead of its time, according to Andrew Yang, Apache Design Solutions Inc. chairman and CEO, but it's important for EDA vendors to get the ball rolling now. Yang said EDA has historically tackled a problem in three stages: analyze, avoid, then fix. EDA needs to start analyzing this problem now, he said.

Yang's company rolled out an integrated electro-thermal tool for analyzing system-on-chip temperature's impact on leakage, timing, reliability and voltage drop last week.

"Are we creating a solution for a problem that doesn't yet exist?" Yang asked. "We have to be ready. We have to be two years ahead of the curve. We need to think about this now."

Three years from now, the semiconductor industry will be talking about fixing the thermal problem, according to Yang, who added that "it is a big problem."

Pitts said that TI, in the short term, can apply a methodology it has developed to leverage models across libraries to calculate thermal effects, such as temperature, voltage and leakage.

"We have some time, and we probably have some measures we can take [to push out the need for thermal analysis EDA tools]," Pitts said. But, he acknowledged, "We are getting to the point that we are going to get a lot of help from the EDA folks. We aren't there yet, but it's just around the corner."

A recent EE Times EDA Users Survey found that, as feature sizes shrink, designers expect that managing leakage current will become their biggest concern. Later, Pitts added, "We've got to find a way to leverage thermal variation across chip," Pitts said. "What we do now is design the whole chip for the worst case scenario."

Rajit Chandra, chief technology officer of Gradient Design Automation, agreed. "Designers effectively assume that a chip has uniform temperature, so they design for average temperature instead of design for temperature peaks," he said.

Worse, Chandra said, aggressive power reduction methods such as voltage island and power gating cause temperature on a chip even more.

Power reduction is the biggest "hammer" for reducing thermal concerns, according to Sri Santhanum, vice president of engineering at PA Semiconductor Inc. Santhanum said his company employs various options for controlling a chip's heat, including system-level design and architectural choices.

Javier De La Cruz of eSilicon Corp., who has spent the bulk of his career with packaging companies, noted that designers often choose packages too early in the design process, selecting a package that will give them an adequate thermal budget for the chip they are designing. But, he said, they fail to consider that the parts will never be sitting alone—they might choose a package that will be right for a standalone IC, but that the chips eventually become part of a system of other components that will ultimately influence the thermal impact.

"As heat goes up, leakage goes up, and hence your heat goes up even more," De La Cruz said. "It's a vicious circle."

The key, De La Cruz argued, is choosing the right package early on through talking with customers, because the wrong decision could be a "very tough thing to change."

The EDA vendors on the panel disagreed with Pitts about the connection between power density and heat in concentrated areas of a chip.

Yang said a common misconception among designers is that the area of a chip that has the highest power density is the area with the highest heat effects. This is not true, he said, because of heat dissipation, heat sinks and other factors.

But TI's Pitts said, respectfully disagreeing with Yang and Chandra, that his next step in combating thermal effects will be to examine power density across designs.

"It will help us," Pitts said. "It is not the final answer. As we get better solutions, we can start to move away from that."

In an interview with EE Times following the panel, Pitts said that thermal impact was contained prior to the 130-nm node by process improvements. At the 90-, 65- and 45-nm nodes, design has stepped in to assist with heat dissipation, he said, including alterations to embedded software, including, for example, a stand-by mode for cell phone operating systems.

The panel, titled "Entering the Hot Zone," was moderated by Daya Nadamuni, research vice president at Gartner Dataquest.