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Hitachi Claims Paper-Thin RFID Chip

The technology can be used as an intelligent watermark, Hitachi says; the company is due to present more details at an IEEE conference this week.
TOKYO — Targeting radio-frequency identification, Hitachi Ltd. has developed what it says is the smallest and thinnest IC in the world for those applications.

Hitachi was due to present details of the 0.15-millimeter by 0.15-millimeter, 7.5-micron-thick chip on Sunday (Feb. 5) at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco.

Paper is typically 80 microns to 100 microns thick, and the chip substrate has been made small and thinned to 7.5 micron to ease application in paper, where it could be used as an intelligent watermark.

Hitachi has been pursuing such “embedded” applications for its “Mu-chip” for years. The company integrated an antenna on an earlier version of the chip in September 2003. In the latest version, the company has reduced the plan dimensions and the thickness of the chip.

"The smallness is one [important] function for an RF IC chip," said Mitsuo Usami, senior chief researcher of Hitachi's Central Research Laboratory, who invented Hitachi's mu-chip initiative. “We fabricated the prototype using technology widely used for volume production."

This time around, the R&D team used silicon on insulator (SOI) technology to create an even smaller version. "When I presented a 0.3-millimeter by 0.3-millimeter chip at ISSCC in 2003, I was thinking about the use of SOI wafers as the next step," said Usami. The 0.3-mm by 0.3-mm chip was 60 microns thick. Using an SOI wafer, which has a thin silicon layer on top of an insulator layer, the Hitachi team fabricated the four-metal-layer CMOS on the SOI wafer and etched from backside to remove the silicon substrate. Etching stops at the insulator layer, leaving the 7.5-micron-thick chip. If a chip were to be made thin by grinding a wafer from the backside, precise control would be required, and it would be impossible to grind a wafer precisely 7.5 microns thick, said Usami. Even though the chip is thinner, it has increased robustness, he said.

In conventional Mu-chip design, a doped guard ring structure was necessary to separate high-frequency elements in the RF IC chip and to prevent interference, but the elements on the SOI wafer can be separated in dedicated wells bounded at the bottom and on the sides by silicon dioxide, which allowed further size reduction.

"I believe that Mu-chip is about two generations in advance of other prototypes," said Usami. Hitachi started offering a 0.4-mm by 0.4-mm Mu-chip in October 2001. It receives 2.45-GHz microwaves with an external antenna for applications in Japan and transmits back a 128-bit ID number. The ID is written into the chip's read-only memory during fabrication. The newly developed 0.15-mm by 0.15-mm chip has the same function and has been shown to work.

Hitachi's first Mu-chip was used for the admission ticket for the 2005 World Exposition, in Aichi, Japan. Compared with that chip, the latest version is nearly one-fifteenth the size. The prototype used a 180-nm process. But when it reaches volume production, the process will shrink along with the industry's road map, Usami said.