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What AMD has here is a failure to communicate. That's the only judgment one can make, in light of the scrappy semiconductor maker's about-face Thursday regarding shipments of its Barcelona quad-core processor, <a href="http://www.informationweek.com/blog/main/archives/2007/09/amd_launches_lo.html">launched on Sept. 10</a>. For the past three months, AMD has downplayed reports of tight supplies and delays in ramping up manufacturing of the cutting-edge chip. Now, the company seems to be simultane
December 7, 2007
5 Min Read
What AMD has here is a failure to communicate. That's the only judgment one can make, in light of the scrappy semiconductor maker's about-face Thursday regarding shipments of its Barcelona quad-core processor, launched on Sept. 10. For the past three months, AMD has downplayed reports of tight supplies and delays in ramping up manufacturing of the cutting-edge chip. Now, the company seems to be simultaneously admitting to a slow ramp while saying nothing's happening that it hadn't already said was happening. Got it?Jeez, my head is hurting already. So here's the deal. On the one hand, AMD says Barcelona shipments are "tracking to guidance" -- i.e., hundreds of thousands of parts are shipping during 4Q of 2007. However, it's also admitting that "our initial ramp of Barcelona had been slower than anticipated."
Thirdly, there's a bug in the first crop of Barcelonas. Here's the explanation, from a statement AMD e-mailed out on Thursday:
"There has been some talk about an erratum relative to our TLB cache in Barcelona as well as Phenom processors resulting in delays. AMD notified customers of this erratum and released a BIOS fix prior to the Nov. 19th launch that resolves it. We are experiencing strong AMD Phenom demand and are shipping parts to channel, system builders and OEM customers.
"Respective to Quad-Core AMD Opteron, we are only shipping processors earmarked for specific end-user installations where customers have had the opportunity to validate the stability and robustness of the solution where it leverages the BIOS fix or some other potential software workarounds. Quad Core AMD Opteron processors shipping for general availability in the Q108 time frame will not have this erratum."
Okay, so the quick and dirty translation of the whole thing is that it's looking like the real manufacturing ramp-up for Barcelona won't occur until 1Q of 2008.
AMD's got some kind of Clintonian parsing of what the words "ramp" or "shipping" mean going on here. Wouldn't it have been far simpler to just say, back in September: "We're announcing Barcelona, there are the usual challenges in ramping up a completely new architecture, and, while we will ship as many parts as we can this year, the real ramp up will take place in 1Q." (Barcelona and its sister Phenom desktop processor are AMD's first quad parts and its first implementation of the new 10h architecture.)
There, that wouldn't have been so hard, would it? I guess you gotta remember that all this evolved in a corporate environment, where everyone had signed on to Chairman Hector Ruiz's and President Dirk Meyer's public commitment to ship Barcelona and Phenom in 2007, and no one wanted to be the one to stand up in a meeting and call bullfeathers on the whole deal.
OK, enough free consulting advice for AMD. Let's move on to the interesting part, which is the erratum that's supposedly at issue here. I say supposedly, because many of yesterday's news reports attribute the Barcelona ramp delays to an arcane bug for which a workaround has already been identified. I should add that it's AMD which is throwing the erratum into the mix as bearing responsibility for the delay.
I Don't Buy It
I don't buy it. (Didn't I say that already.) The translation-lookaside buffer bug which seems to be at issue is a fairly obscure one, not a showstopper, by any means.
Going to the videotape, I think the erratum at issue is number 122 in the latest AMD documentation I've been able to dig up. It's identified as "TLB Flush Filter May Cause Coherency Problem in Multicore Systems."
Here's the description:
"Under highly specific internal timing conditions in system configurations that include more than one processor core, coherency problems may arise between the page tables in memory and the translations stored in the on-chip TLB. This can result in the possible use of stale translations even after software has performed a TLB flush."
Obscure enough for you?
My take is that Barcelona and Phenom are simply ramping up slowing because AMD is having yield issues at the Dresden fab where it's making the parts. It's had these issues since much earlier this year, when reports first surfaced that the initial Barcelonas weren't running faster than 2.0 GHz. Such a problem could be a design flaw, which would be very serious if that were the case. At first glance, though, not getting your speed grades off of the fab is a yield problem indicative of ramp-up issues.
The other question which ties in with this is, why does there seem to be a trickle (or, "hundreds of thousands"; same thing) of Barcelonas, but no Phenoms? True, AMD has said there won't be Phenoms in quanitity until 1Q. However, this staged roll-out plan also seems to tie in with a scenario where Barcelona is being buzzed out first (with the plan that the Phenom ramp would follow). It's probably the case that what happened is, the manufacturing of Barcelona has turned out to be much more of a bear than anyone anticipated.
I suspect that this has been going on for a quite a while, and that AMD's process engineers are under the gun to make sure that the huge quanitities of both Barcelona and Phenom are rolling off the fabs next year. I'd wish those guys a Merry Christmas, but I'm guessing they're gonna be working for the duration.
P.S. Read my deep dive into the new processors, in Inside AMD's Phenom And Opteron Quad-Core Architectures.
P.P.S. Read my follow-up post, Bug In AMD's Quad-Core Barcelona And Phenom May Be More Serious Than Previously Suspected
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