Indian Researchers Unveil Processor Test Framework

BANGALORE, India — Researchers from the Indian Institute of Technology in Chennai and Intel's validation and test solutions center at Austin have teamed to unveil a unified framework for generating functional tests for processors, at the recent VLSI Design and Test 2006 conference in Goa in western India.

"The framework can be used to generate directed test for functional verification of processors, at different levels, namely, the Instruction Set Architecture to Micro-architecture, and also combinations of them," the paper said. "A constraint solver-based approach is employed in the framework. The effectiveness of the framework is demonstrated by developing the same using the ILOG Constraint Solver and plugging-in Cache and Translation Look-aside Buffer (TLB) models into it," the paper added.

One benefit of the framework is the plug-and-remove feature it offers for different modules, useful for evolving designs where design development and verification are done concurrently, the paper said.

The methodology proposed is scalable with the design size, as this involves development of constraint model-based on the design specification, which is at a higher level of abstraction. The constraint model thus designed is an integration of several sub modules which are derived, based on the functionalities of the design, such as the TLB, cache, and branch predictor, which leads to a natural partitioning of top-level constraint model, aiding scalability.