MIT Research Looks To Extend Moore’s Law

For years the semiconductor world has waited for Moore's Law to reach its limit. However, new research from MIT shows how manufacturers can shrink geometries past 20 nm cost-effectively.

Ismini Scouras, Contributor

February 28, 2014

1 Min Read

Despite skepticism in the chip industry that Moore's Law could be reaching its limits, MIT Researchers believe that they have found a way to enable semiconductor manufacturers to continue shrinking geometries below 20 nanometer and produce advanced components cost-effectively.

MIT researchers have developed directed self-assembly (DSA) techniques that they claim resolve the issues associated with the two main lithography techniques used in the semiconductor manufacturing process today -- photolithography and electron-beam lithography. Photolithography at 193 nm is reaching its limit with feature sizes around 25 nm. And the throughput in electron-beam lithography, which can produce smaller features, is insufficient for sub-20-nm resolution pattering over large areas.

Described as a hybrid process, the DSA technique is based on a simplified template in which complex patterns of line, bends, and junctions with feature sizes below 20 nm can be made using block copolymer self-assembly, according to the MIT study. It also explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. DSA can be five or more times faster than writing the entire pattern by electron beam lithography, according to the MIT study.

"DSA is of great interest to manufacturers as scaling using traditional patterning techniques has become increasingly more challenging and costly," said Bob Havermann, director of nanomanufacturing sciences at Semiconductor Research Corp., Research Triangle Park, N.C., which sponsored the MIT report.

Read the rest of this article on EE Times.

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