The new technique has the potential of paving the way for next-generation computer components that deliver higher performance at the same or less power than current technology. This is the result of being able to pack more circuitry on the same size surface. In addition, the technique could be used in the development of circuitry for other applications, such as solar cells.
Specifically, MIT researchers have been able to etch 25-nanometer wide electron-carrying paths that are 25 nanometers apart. A nanometer is one billionth of a meter. The thinnest circuitry available today in general microprocessors that are the brains of home and business computers is 45 nanometers. Intel, which started shipping such products late last year, leads the industry. Rival Advanced Micro Devices is expected to ship 45-nm CPUs this year.
The accomplishment of the MIT team is not in the size, but in the fact that it can etch precise patterns of 20,000 lines per millimeter using less expensive infrastructure than what's used in building today's processors, Ralf Heilmann, a lead researcher on the MIT team, told InformationWeek.
The process of etching the paths, or lines, of circuitry on silicon starts with a process similar to photography, where light is shined through a negative onto photosensitive paper, creating a pattern. In a process called nanolithography, chipmakers pass light through a mask onto a photosensitive "resist," which is a thin polymer, and then place the material on a piece of silicon as a circuitry pattern.
Today, chemically amplified resists are used to accommodate the short wavelengths of light needed to draw such thin lines. The MIT method, however, uses a relatively long 351-nm wavelength that doesn't need the chemical crutch, Heilmann said.
The new line-drawing method is similar to using a comb with three of every four teeth missing to draw lines in the sand. MIT researchers can move the comb over one line at a time to fill in the gaps, using sound waves as a guide. The tool developed for the process is called a nanoruler.
The technique was developed out of the university's need to keep infrastructure costs down, since it works with a smaller budget than commercial chipmakers. "In a university environment, we're limited to relatively low-cost approaches to these problems," Heilmann said. "What the industry might be interested in doing is commingling our approach with all the infrastructure that they have and push things even further."
To shrink circuitry further, researchers are focusing on the materials used for the etchings. The thinner the line the more difficult it is using today's materials to draw lines perfectly straight. "The line can get so wiggly that it is not there anymore," Heilmann said. "It's cut or interrupted."
The MIT team conducted its research in the Space Nanotechnology Laboratory at the university's Kavli Institute of Astrophysics and Space Research. Funding came from NASA and the National Science Foundation. Results of the research have been published by the journal Optics Letter and were recently presented at the International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication in Portland, Ore.