IBM, Micron Go 3-D To Boost Memory Performance - InformationWeek

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12/2/2011
04:26 PM
Art Wittmann
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IBM, Micron Go 3-D To Boost Memory Performance

A new manufacturing technique results in faster I/O, less power consumption, and decreased footprint.

Ask any theoretical cosmologist about space travel and they'll tell you it's easy. Just pick where you want to go in the universe, then fold space so that point is near you, and then just jump between the folds. While it's conceptually easy, no one really knows how to fold space or how to jump from one fold to another (Dune fans, no need to write in about the spice mines of Arrakis--I know). A similar dilemma has faced chip makers.

If you imagine yourself the size of a transistor, a modern-day memory chip is a sprawling thing, sort of like Phoenix in the desert, and getting from one end to the other just takes a long time. What if you could take Phoenix and fold it up like a map? If you could then jump between the folds of the map, you could get across town in an instant. The same is true for memory chips. If they were built in layers, performance could be dramatically improved and, by going vertical, you'd fit far more transistors in far less space. The only problem is how to do it.

Micron's Hybrid Memory Cube
(click image for larger view)
Micron's Hybrid Memory Cube

IBM has solved the problem with what it calls through-silicon vias (TSVs). Vias are signal paths built between layers of silicon. They allow memory chips to essentially be stacked on top of each other reducing the surface area of the chip, while also reducing time for signal propagation across the chip. IBM has teamed with Micron to create the Hybrid Memory Cube, which the companies claim will be up to 15 times faster than present technology.

[ Intel's 3-D transistors offer a different take on going vertical. Read Why Do Intel's 3-D Transistors Matter?. ]

Prototypes of the HMC have been produced that deliver bandwidth of 128 gigabytes per second whereas the state of the art is 1/10 that. The HMC chips draw just 70% of the power of conventional architectures, and the chips themselves have a footprint just 10% the size of current chips. The technology will first make its way into high-performance computing machines, but will eventually work its way into other uses.

IBM also expects to use the technology for more than memory chips, with other applications coming to market over the next few years. This first round of devices will be made in IBM's East Fishkill plant using the company's 32nm, high-K metal gate process.

Art Wittmann is director of InformationWeek Reports, a portfolio of decision-support tools and research reports. You can write to him at [email protected].

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